1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) capable of reducing potential deviation of a common electrode of a panel by forming the common electrode to have a mesh structure, and also capable of restraining the reduction of an aperture ratio.
2. Description of the Related Art
Recently, in line with the rapid development of an information and communication sector, the importance of the display industry for displaying desired information is increasing, and, among display devices up to date, the CRTs (Cathode Ray Tubes) have been much popular because of its advantages of displaying various colors and exerting bright screen image.
However, the desires for a display which is large and portable and has high resolution urgently request development of a flat panel display instead of the heavy and voluminous CRTs. Such flat panel display can be variably and extensively applied from computer monitors to aircrafts, spacecrafts, etc.
Currently manufactured or developed flat panel displays include a liquid crystal display (LCD), an electroluminescent display (ELD), a field emission display (FED), a plasma display panel (PDP), or the like.
An ideal flat panel display would have such characteristics that it is light, has high luminance, high efficiency, high resolution, a fast response characteristics, is driven at a low voltage, consumes less power, incurs a low cost, and has natural color display characteristics, etc.
Among the flat panel displays, the LCD receives much attention as it meets the demands and has durability and portability.
In general, the LCD is an image display device using optical anisotropy characteristics of liquid crystal. That is, light is irradiated to liquid crystal having polarization characteristics according to a voltage applied state, and the amount of light that passes through the liquid crystal is controlled according to an alignment state of the liquid crystal according to an applied voltage to thus display an image.
To configure the LCD, a liquid crystal panel including a liquid crystal layer and a circuit which is provided near the liquid crystal panel to apply signals to the liquid crystal panel and control the signals are required.
The related art in-plane switching (iPS) mode LCD will now be described with reference to FIG. 1.
FIG. 1 is a plan view schematically showing the related art IPS mode LCD.
With reference to FIG. 1, the related art IPS mode LCD includes a plurality of gate lines 23 and a plurality of data lines 23 vertically and horizontally to define pixel areas (not shown), a common line 15 arranged to be parallel to the gate line 13, and a plurality of common electrodes 29a and 29b connected to the common line 15 and formed to be parallel to the data line 23.
In addition, a thin film transistor (TFT), including a gate electrode (not shown), a gate insulating layer (not shown), a semiconductor layer (not shown) and source and drain electrodes 23a and 23b, is formed at each crossing of the gate lines 13 and the data lines 23.
Pixel electrodes 27 are formed to be connected to the drain electrode 23b and formed between the common electrodes 29b at each pixel area.
In the pixel area, the pixel electrode 27 and the common electrode 29 are formed to be parallel to the data line 23, and a horizontal electrode portion 27a of the pixel electrode 27 overlaps with the common line 15 to form a storage capacity.
Accordingly, when a data voltage is applied via the TFT, an in-plane field (horizontal field) is formed between the common electrode 29 and the pixel electrode 27.
A connection structure of the common electrode and the data line will now be described with reference to FIGS. 2 and 3.
FIG. 2 is a sectional view taken along line II-II in FIG. 1, and FIG. 3 is a sectional view taken along line III-III in FIG. 1.
With reference to FIGS. 2 and 3, in the related art LCD, the gate line (13 in FIG. 1), a gate electrode (not shown), the common line 15 and the common electrode 29b are formed on a lower substrate 11. A gate insulating layer 17 is formed on the entire surface of the substrate including the gate line and the common line, and a semiconductor layer (not shown) is formed on the gate insulating layer 17 at an upper side of the gate electrode (not shown).
In addition, on the gate insulating layer 17, there are formed the data lien 23, source and drain electrodes 23a and 23b, and the pixel electrode 27 such that the are perpendicular to the gate line 13, and a protection layer 25 is formed between the source and drain electrodes 23a and 23b and the pixel electrodes 27.
Although not shown, a black matrix layer (not shown) is formed at portions excluding the pixel areas on an upper substrate facing the lower substrate 11, and a color filter layer (not shown) is formed at each pixel area.
A liquid crystal layer (not shown) is formed between the upper substrate including the color filter layers (not shown) and the lower substrate 11.
Accordingly, when a data voltage is applied to the pixel electrode 27, an in-plane field is formed due to a voltage difference between the pixel electrode 27 and the common electrode 29, and the liquid crystal can be aligned by the in-plane field.
The related art IPS mode LCD has the following problems.
A coupling phenomenon occurs at the common electrodes or the common lines overlapping with the data lines, causing a defective screen image.
In addition, if ripples are generated due to a coupling capacitance of signals of the common electrode Vcom, a potential deviation of the common electrodes (Vcom) in the panel increases.